technical data KK74ACT652 octal 3-state bus transceivers and d flip-flops high-speed silicon-gate cmos ordering information kk 74act652n plastic kk 74act652dw soic t a = -40 to 8 5 c for all packages the kk 74act652 is identical in pinout to the ls/als652, hc / h c t 652. the kk 74act652 may be used as a level converter for interfacing ttl or nmos outputs to high speed cmos inputs. these devi ces consi s t s of bus t r anscei ver ci rcui t s , d-t y pe fl i p -fl op, an d co n t ro l circu itry arran g e d fo r m u ltip lex tran sm issio n o f d a ta d i rectly from t h e dat a bus or from t h e i n t e rnal st orage regi st ers. di rect i on and out put enabl e are provi ded t o sel ect t h e read-t i m e or st ored dat a funct i on. dat a on t h e a or b dat a bus, or bot h, can be st ored i n t h e i n t e rnal d fl i p - fl ops by l o w-t o -hi gh t r ansi t i ons at t h e appropri a t e cl ock pi ns (a-t o-b c l ock or b - t o -a c l ock) regardl e ss of t h e sel ect or enabl e or enabl e cont rol pi ns. w h en a-t o -b source and b-to-a source are in th e real-tim e t r ansfer m ode, i t i s al so possi bl e t o st ore dat a wi t hout usi ng t h e i n t e rnal d-t y pe fl i p -fl ops by si m u l t a neousl y enabl i ng di rect i on and out put enable. in this configuration each out put reinforces its input. thus, when al l ot her dat a sources t o t h e t w o set s of bus l i n es are at hi gh i m pedance, each set of bus lines will rem a in at its last state. the kk 74act652 has noninverted outputs. ? ttl/nmos com p atible input levels ? outputs directly interf ace to cmos, nmos, and ttl ? operat i ng vol t a ge r a nge: 4.5 t o 5.5 v ? low input c u rrent : 1.0 a; 0.1 a @ 25 c ? out put s source/ si nk 24 m a pin assignment logic diagram pin 24=v cc pin 12 = gnd 1
KK74ACT652 maximum ratings * sym b o l p a r a m e t e r valu e un i t v cc dc suppl y vol t a ge (referenced t o gnd) -0.5 t o +7.0 v v in dc input vol t a ge (referenced t o gnd) -0.5 t o v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input c u rrent , per pi n 20 ma i out dc out put si nk/ source c u rrent , per pi n 50 ma i cc dc suppl y c u rrent , v cc and gnd pins 50 ma p d po wer dissip a tio n in still air, plastic dip+ soic package+ 750 500 mw tst g st orage tem p erat ure -65 t o +150 c t l lead tem p erat ure, 1 m m from c a se for 10 seconds (plastic dip or soic package) 260 c * m a xi m u m r a t i ngs are t hose val u es bey ond whi c h dam a ge t o t h e devi ce m a y occur. functional operation should be restricted to the reco m m e nded operating conditions. +derat i ng - pl ast i c dip: - 10 m w / c from 65 t o 125 c soic package: : - 7 m w / c from 65 t o 125 c recommended operating conditions sy m bol p a r a m e t e r m i n m a x uni t v cc dc suppl y vol t a ge (referenced t o gnd) 4.5 5.5 v v in , v out dc input vol t a ge, out put vol t a ge (referenced t o gnd) 0 v cc v t j junct i on tem p erat ure (pdip) 140 c t a operating tem p erature, all package types -40 +85 c i oh out put c u rrent - hi gh -24 m a i ol out put c u rrent - low 24 m a t r , t f input r i se and fal l ti m e * (except schm itt inputs) v cc =4.5 v v cc =5.5 v 0 0 10 8.0 ns/ v * v in from 0.8 v t o 2.0 v thi s devi ce cont ai ns prot ect i on ci rcui t r y t o guard agai ns t dam a ge due t o hi gh st at i c vol t a ges or el ect ri c fi el ds. however, precautions m u st be taken to avoid applications of any voltage highe r than m a xim u m rated voltages to this hi gh-i m pedance ci rcui t . for proper operat i on, v in and v out shoul d be const r ai ned t o t h e range gnd (v in or v out ) v cc . unused i nput s m u st al way s be t i e d t o an appropri a t e l ogi c vol t a ge l e vel (e.g., ei t h er gnd or v cc ). unused out put s m u st be l e ft open. 2
KK74ACT652 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed lim its sy m bol p a r a m e t e r test c ondi t i o n s v 25 c - 4 0 c to 85 c un it v ih m i ni m u m hi gh- level input vol t a ge v out =0.1 v or v cc -0.1 v 4.5 5.5 2.0 2.0 2.0 2.0 v v il m a x i mu m l o w - level input vol t a ge v out =0.1 v or v cc -0.1 v 4.5 5.5 0.8 0.8 0.8 0.8 v v oh m i ni m u m hi gh- level out put vol t a ge i out -50 a 4.5 5.5 4.4 5.4 4.4 5.4 v * v in =v ih or v il i oh =-24 m a i oh =-24 m a 4.5 5.5 3.86 4.86 3.76 4.76 v ol m a x i mu m l o w - level out put vol t a ge i out 50 a 4.5 5.5 0.1 0.1 0.1 0.1 v * v in =v ih or v il i ol =24 m a i ol =24 m a 4.5 5.5 0.36 0.36 0.44 0.44 i in m a xi m u m input leakage current v in =v cc or gnd 5.5 0.1 1.0 a ? i cct addi t i onal m a x. i cc / i nput v in =v cc - 2.1 v 5.5 1.5 m a i oz m a x i mu m t h r e e - state leakage current v in (oe)= v ih or v il v in =v cc or gnd v out =v cc or gnd 5.5 0.6 6.0 a i old +min im u m dyn a m i c out put c u rrent v old =1.65 v m a x 5.5 75 m a i ohd +min im u m dyn a m i c out put c u rrent v ohd =3.85 v m i n 5.5 -75 m a i cc m a x i mu m q u i e s c e n t suppl y c u rrent (per package) v in =v cc or gnd 5.5 8 .0 80 a * al l out put s l o aded; t h reshol ds on i nput associ at ed wi t h out put under t e st . +m axi m um t e st durat i on 2.0 m s , one out put l o aded at a t i m e. 3
KK74ACT652 ac electrical characteristics (v cc =5.0 v 10%, c l =50pf,input t r =t f =3.0 ns) g u a r a n t e e d lim i t s sym b o l p a r a m e t e r 25 c - 4 0 c to 8 5 c un it min m ax min max t plh propagat i on del a y , a-t o -b c l ock or b - t o -a c l ock t o a or b dat a port (fi gure 1) 4 . 0 1 4 . 5 3 . 5 1 6 . 5 n s t phl propagat i on del a y , a-t o -b c l ock or b - t o -a c l ock t o a or b dat a port (fi gure 1) 3 . 5 1 4 . 5 3 . 0 1 6 . 5 n s t plh propagat i on del a y , input a t o out put b or input b t o out put a (fi gures 2,3) 2 . 5 1 1 . 5 2 . 0 1 3 . 0 n s t phl propagat i on del a y , input a t o out put b or input b t o out put a (fi gures 2,3) 2 . 5 1 1 . 5 2 . 0 1 3 . 0 n s t plh propagat i on del a y , a-t o -b source or b - t o -a source t o a or b dat a port (fi gure 4) 2 . 5 1 2 . 0 2 . 0 1 3 . 5 n s t phl propagat i on del a y , a-t o -b source or b - t o -a source t o a or b dat a port (fi gure 4) 3 . 0 1 2 . 0 2 . 5 1 3 . 5 n s t pzh propagat i on del a y , out put enabl e t o a dat a port (fi gure 5) 2 . 0 1 1 . 5 1 . 5 1 3 . 0 n s t pzl propagat i on del a y , out put enabl e t o a dat a port (fi gure 5) 2 . 5 1 1 . 5 2 . 0 1 3 . 0 n s t phz propagat i on del a y , out put enabl e t o a dat a port (fi gure 5) 3 . 0 1 3 . 0 2 . 5 1 4 . 0 n s t plz propagat i on del a y , out put enabl e t o a dat a port (fi gure 5) 2 . 5 1 2 . 5 2 . 0 1 4 . 0 n s t pzh propagat i on del a y , di rect i on t o b dat a port (fi gure 6) 2 . 5 1 2 . 0 2 . 0 1 3 . 5 n s t pzl propagat i on del a y , di rect i on t o b dat a port (fi gure 6) 2 . 5 1 2 . 0 2 . 0 1 3 . 5 n s t phz propagat i on del a y , di rect i on t o b dat a port (fi gure 6) 3 . 5 1 3 . 5 3 . 0 1 4 . 5 n s t plz propagat i on del a y , di rect i on t o b dat a port (fi gure 6) 3 . 0 1 3 . 5 2 . 5 1 5 . 0 n s c in m a xi m u m input c a paci t a nce 4.5 4.5 pf c out input / o ut put c a paci t a nce 15 15 pf typical @25 c,v cc =5.0 v c pd power di ssi pat i on c a paci t a nce 60 pf 4
KK74ACT652 timing requirements (c l =50pf,input t r =t f =3.0 ns) v cc * guaranteed lim its sym b o l p a r a m e t e r v 25 c - 4 0 c to 85 c unit t su m i ni m u m set up ti m e , a or b dat a port t o a- t o -b c l ock or b - t o -a c l ock (fi gure 7) 5.0 7 . 0 8 . 0 n s t h m i ni m u m hol d ti m e , a-t o -b c l ock or b - t o -a c l ock t o a or b dat a port (fi gure 7) 5.0 2 . 5 2 . 5 n s t w m i ni m u m pul s e w i dt h, a-t o -b c l ock or b - t o -a c l ock (fi gure 7) 5.0 6 . 0 7 . 0 n s timing diagram 5
KK74ACT652 function table d i r . o e c a b cba s a b s b a a b f u n c t i o n inputs inputs b o t h t h e a bus and t h e b bus are i nput s. l h x x x x z z the out put funct i ons of t h e a and b bus are disabled. x x inputs inputs b o t h t h e a and b bus are used for i nput s to th e in tern al flip -flo p s . data at th e b u s will b e sto r ed o n lo w to h i g h tran sitio n o f t h e cl ock i nput s. outputs inputs the a bus are out put s and t h e b bus are i nput s. x * x x l l h l h the data at the b bus are displayed at the a bus. l l x * x l l h l h the data at the b bus are displayed at the a bus. the dat a of t h e b bus are st ored t o th e in tern al flip -flo p s o n lo w to h i g h t r ansi t i on of t h e cl ock pul se. x * x x h qn x th e d a ta sto r ed to th e in tern al flip -flo p s , are displayed at the a bus. x * x h h l h l the data at the b bus are stored to the in tern al flip -flo p s o n lo w to h i g h t r ansi t i on of t h e cl ock pul se. the st at es of th e in tern al flip -flo p s o u t p u t d i rectly to t h e a bus. inputs outputs the a bus are i nput s and t h e b bus are out put s. x x * l x l h l h the data at the a bus are displayed at the b bus. h h x * l x l h l h the data at the b bus are displayed at the a bus. the dat a of t h e b bus are st ored t o th e in tern al flip -flo p s o n lo w to h i g h t r ansi t i on of t h e cl ock pul se. x x * h x x qn th e d a ta sto r ed to th e in tern al flip -flo p s are displayed at the b bus. x * h x l h l h the data at the a bus are stored to the in tern al flip -flo p s o n lo w to h i g h t r ansi t i on of t h e cl ock pul se. the st at es of th e in tern al flip -flo p s o u t p u t d i rectly to t h e b bus. outputs outputs b o t h t h e a bus and t h e b bus are out put s h l x x h h q n q n the data stor ed to th e in tern al flip -flo p s are di spl a y e d at t h e a and b bus respectively. h h qn qn the out put at t h e a bus are di spl a y e d at t h e b bus, t h e out put at t h e b bus are di spl a y e d at t h e a bus respec. x : don?t care z : high im pedance qn : the data stored to the internal flip-f lops by m o st recent low to high transition of the clock inputs * : the data at the a and b bus w i ll be stored to the internal flip-flops on every low to transition of the clock inputs 6
KK74ACT652 switching diagrams fi gure 1. sw i t chi n g waveforms figure 2. a data port = input, b data port = output figure 3. a data port = output, b data port = input fi gure 4. sw i t chi n g waveforms fi gure 5. sw i t chi n g waveforms fi gure 6. sw i t chi n g waveforms fi gure 7. sw i t chi n g waveforms 7
KK74ACT652 expanded logic diagram 8
KK74ACT652 n s u f f i x p l as t i c d i p (m s - 0 0 1 a f ) sy m b o l m i n m a x a 3 1. 24 3 2 . 5 1 b 6 . 1 7. 11 c5 d 0 .3 6 0 .5 6 f 1 .1 4 1 .7 8 g h j0 10 k 2 .9 2 3 .8 1 no t e s : l 7 .6 2 8 .2 6 1. d i m e n s i o n s ?a ?, ?b ? d o n o t i n cl u d e m o l d f l as h o r p r o t r u s i o n s . m 0 . 2 0. 36 m a x i m u m m o l d f l a s h o r p r o t r u s i o n s 0. 25 m m ( 0 . 010) p e r s i d e . n0 . 3 8 d su f f i x so i c (m s - 0 1 3 a d) sy m b o l m i n m a x a 1 5. 2 1 5. 6 b7 . 4 7 . 6 c 2 .3 5 2 .6 5 d 0 .3 3 0 .5 1 f 0 . 4 1. 27 g h no t e s : j0 8 1. d i m e ns i o ns a a n d b d o no t i n c l ud e m o l d f l a s h o r p r ot r u s i o n . k0 . 1 0 . 3 2. m a x i m u m m o l d f l a s h o r p r o t r u s i o n 0. 15 m m ( 0 . 006) p e r s i d e m 0 .2 3 0 .3 2 fo r a ; fo r b ? 0. 25 m m ( 0 . 010) p e r s i d e . p 1 0 1 0. 65 r 0 .2 5 0 .7 5 9. 53 d i me n s i o n , mm d i me n s i o n , mm 2. 54 7. 62 1. 27 . 3 3 a b h c k c m j f m p g d r x 45 se a t i n g pl a n e 0 . 25 ( 0 . 0 10 ) m t -t - 1 24 12 13 l h m j a b f g d se a t i n g pl a n e n k 0. 2 5 ( 0 . 010 ) m t -t - c 1 24 12 13 9
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